Sequential comparison ADC (Analog to Digital Converter) is one type of A/D (analog/digital) conversion system. High-speed and high-accuracy AD (analog to digital) conversion has become possible by way of CMOS process miniaturization so that sequential comparison ADC is now utilized in a wide range of fields from conventional sensor applications to wireless communications, etc. Among these fields, sequential comparison ADC that performs non-binary conversion has, proven particularly resistant (robust) to unwanted effects such as device mismatches caused by process miniaturization and so research in this area has been reported in academic conferences in recent years.
In binary sequential comparison ADC of the related art is based on binary search, digital values are decided by a binary search performed in order from high-order bits while applying feedback to the analog signal that is input in the DAC (Digital to Analog Converter). The weight of each bit is therefore applied at a power of 2. In other words, the relation between the digital output value x and each bit Di from the AD conversion results is given by the following formula.
                    x        =                              ∑                          i              =              0                                      N              -              1                                ⁢                                    2              i                        ⁢                          D              i                                                          [                  Formula          ⁢                                          ⁢          1                ]            
In some cases, Di={0,1} and Di={−1, +1} according to the notation method but are still essentially the same. Unless stated to the contrary, the notation Di {−1, +1} is utilized here.
In non-binary ADC however the weight of each bit is given by ADC that is not a power of 2. Namely, in non-binary ADC, the relation between the digital output x and each bit Di in the AD conversion results is given in the following formula.
                    x        =                              ∑                          i              =              0                                      N              -              1                                ⁢                                    W              i                        ⁢                          D              i                                                          [                  Formula          ⁢                                          ⁢          2                ]            
Here, Wi is the weighting coefficient and is typically a value differing from 2i. The non-binary ADC can usually be configured by selecting Wi+1/Wi<2 so that there are plural AD conversion results relative to the analog value. The presence of plural AD conversion results in other words signifies that there are plural search routes, forming this type of structure allows redundancy in the conversions.
Correct AD conversion results can therefore be obtained due to redundancy even if a conversion error occurs in the process for sequential comparison due to noise in the comparator or an incomplete setting for feedback DAC.
However in non-binary ADC, unless the coefficient of the feedback DAC matches the value of the weighted coefficient Wi, the AD conversion accuracy will deteriorate due to errors occurring in the digital output value.
A weighting coefficient Wi must be accurately calculated in order to perform accurate AD conversion to cope with fluctuation in the feedback DAC coefficient relative to the design value due to production variations, power supply voltage, and operating temperature, etc. In particular, in order to maintain an optimum value for the weighting coefficient Wi for coping with fluctuations during circuit usage such as the power supply voltage, and operating temperature, the search for the weighting coefficient must be performed in parallel with circuit operation or in other words, a background operation is required.
To meet this need, a method utilizing the LMS (Least-Mean-Square) algorithm is known as a method to find the weighting coefficient of the non-binary ADC. The LMS algorithm is a calculation method that is one type of so-called adaptive algorithm that generates an error signal and sets a weighting coefficient so that the generated error signal approaches zero.
The non-patent documents 1 through 4 each disclose an A/D converter circuit that applies the LMS algorithm. The A/D converter circuit is comprised of an A/D converter unit to convert the analog input signals into digital values, and a corrector unit to digitally correct the output of the A/D converter unit. These non-patent documents 1 through 4 propose a low power consumption, and high-speed and high-accuracy A/D converter circuit that performs digital correction by applying a LMS algorithm in the corrector unit.
[Non-Patent Document 1]
T. Oshima, et al., “Fast nonlineardeterministic calibration of pipelined A/D converters,” IEEE 2008 Midwest Symposiumon Circuits and Systems, Session C2L-C-1, August 2008.
[Non-patent document 2]
T. Oshima, et al., “23-mW 50-MS/s10-bit pipeline A/D converter with nonlinear LMS foreground calibration,” 2009 International Symposium on Circuits and Systems, pp. 960-963, May 2009.
[Non-Patent Document 3]
J. Mcneill, et al., “A split-ADC architecture for deterministic digital background calibration of a 16b 1MS/s ADC,” IEEE2005 International Solid-State Circuits Conference, pp. 276-277, February 2005.
[Non-Patent Document 4]
W. Liu et al., “A 12b 22.5/45MS/s3.0 mW 0.059 mm2 CMOS SAR ADC achieving over 90 dB SFDR,” IEEE 2010 International Solid-State Circuits Conference, pp. 380-381, February 2010.